The present invention generally relates to semiconductor devices and more particularly to a so-called reference cell type semiconductor memory device for storing data in a memory cell, wherein the content of the data stored in the memory cell is identified by comparing an output of the memory cell with an output of a reference cell.
In the field of the semiconductor memory devices such as the non-volatile semiconductor memory devices in particular, so-called reference cell type memory devices are used for reducing the access time. In such a reference cell type memory devices, the identification of the data stored in the memory cell is made on the basis of comparison with the output of a reference cell.
In such non-volatile, reference cell type semiconductor memory devices, efforts are made to increase the integration density, and the size of the transistors forming the memory cells is miniaturized more and more. The transistors forming the reference cells are no exception. In such a non-volatile semiconductor device, there arises a problem such that the size of the transistors forming the reference cells tends to be varied particularly with respect to the gate length, gate width and the like depending on the fabrication process. In the transistors having an extremely miniaturized size, small variation in the gate length, gate width, etc. may cause a significant change in the device characteristic of the transistor.
FIG. 1 shows an example of a conventional erasable programmable read-only memory (EPROM). The memory device comprises a memory part 1 including a memory cell, a reference part 2, and an output part 3, wherein the reading of data from the memory cell is made on the basis of comparison of an output voltage V.sub.M of the memory part 1 with a reference voltage V.sub.R produced by the reference part 2.
Referring to FIG. 1, the memory part 1 includes a p-channel MOS transistor 11 acting as a load resistance, an n-channel MOS transistor 12 for bit line biasing to be described later, an n-channel MOS transistor 13 for the column selection, and a memory cell 14 made of a floating gate type MOS transistor and acting as the memory cell. The MOS transistor 11 has its source connected to a power terminal 15 to which a drain voltage V.sub.DD of typically 5 volts is applied. Further, the MOS transistor 11 has a gate connected to an output terminal 16 of the memory part 1. The MOS transistor 11 has a source connected to its gate and the source of the MOS transistor 11 is connected further to a source of the MOS transistor 12. This MOS transistor 12 is used for biasing a bit line BL which is connected to a source of the memory cell 14 such that the injection of electrons into the floating gate of the memory cell 14 does not occur at the time of reading the data. For this purpose, a gate voltage of 1.2 volts is applied to the gate of the MOS transistor 12 via an input terminal 17 and in response thereto, the voltage of the bit line BL is set to be 0.9 volts. Thereby, the source voltage of the memory cell 14 is also set to be 0.9 volts. The MOS transistor 12 has its drain connected to the source of a MOS transistor 13 which is used for the column selection.
The MOS transistor 13 has a gate connected to the column bus 18 and a drain connected to the source of the memory cell 14 via the bit line BL. Thereby, the MOS transistor 13 supplies the foregoing bit line voltage to the drain of the memory cell 14 via the bit line BL in response to a column selection signal on the column bus 18. The memory cell 14 is made of a floating gate type MOS transistor having a floating gate and a control gate wherein the control gate is connected to the word line WL. The memory cell 14 further has a drain which is connected to the ground and stores the logic data "0" in response to the injection of the electrons into the floating gate. When the electrons are not injected, the memory cell 14 stores the logic data "1". When the memory cell 14 stores the data "0", the MOS transistor forming the cell 14 is turned off even when the word line voltage is supplied to the gate via the word line WL while when the logic data "1" is stored, the MOS transistor 14 is turned on in response to the word line voltage.
The MOS transistor 11 acting as the load resistance is fabricated to have a gate width such that a voltage of 4 volts appears at the output terminal 16 as the output voltage V.sub.M when the addressed memory cell 14 stores the logic data "0" while an output voltage of 3 volts appears at the output terminal 16 when the logic data "1" is stored in the memory cell 14.
The reference part 2 includes a p-channel MOS transistor 21 acting as a load resistance, an n-channel MOS transistor 22 for bit line biasing to be described later, an n-channel MOS transistor 23 for the column selection, and a memory cell 24 made of a floating gate type MOS transistor and acting as the memory cell. The MOS transistor 21 has its drain connected to a power terminal 25 to which the source voltage V.sub.DD of typically 5 volts is applied. Further, the MOS transistor 21 has a gate connected to an output terminal 26 of the reference part 2. The MOS transistor 21 has a source connected to its gate and the drain of the MOS transistor 21 is connected further to a source of the MOS transistor 22. This MOS transistor 22 is used for biasing a bit line BL.sub.R which is connected to a source of the memory cell 24 such that the injection of electrons into the floating gate of the memory cell 24 does not occur at the time of reading the data. For this purpose, a gate voltage of 1.2 volts is applied to the gate of the MOS transistor 22 via an input terminal 27 and in response thereto, the voltage of the bit line BL is set to be 0.9 volts. Thereby, the source voltage of the memory cell 24 is also set to be 0.9 volts. The MOS transistor 22 has its drain connected to the source of a MOS transistor 23 which is used for the column selection.
The MOS transistor 23 has a gate connected to the source voltage V.sub.DD and a drain connected to the source of the memory cell 24 via the bit line BL.sub.R and supplies the foregoing bit line voltage of 0.9 volts to the source of the memory cell 24. The memory cell 24 is made of a floating gate type MOS transistor similarly to the memory cell 14 and has a control gate connected to the word line WL in addition to the floating gate. The memory cell 24 further has a drain which is connected to the ground and stores the logic data "1". In response to the data "1" stored in the memory cell 24, the MOS transistor forming the cell 24 is turned on. It should be noted that the MOS transistor of the memory cell 24 is always biased by the source voltage V.sub.DD supplied to its gate.
The MOS transistor 21 acting as the load resistance is fabricated to have a gate width such that a voltage of 3.5 volts appears at the output terminal 26 as the output voltage V.sub.R. This voltage of 3.5 volts is the voltage intermediate between the voltage of 4.0 volts which is the value of V.sub.M for the case where the data "0" is stored in the cell 14 and 3.0 volts which is the value of V.sub.M for the case where the data "1" is stored in the memory cell 14. The foregoing relationship between the voltage V.sub.M and the voltage V.sub.R may be obtained by setting the gate width of the MOS transistor 21 twice as large as the gate width of the MOS transistor 11 when the memory cell 14 and the memory cell 24 have a same size with respect to the gate length, gate width and the like.
The output circuit part 3 includes a differential amplifier 31 having an inverting input terminal connected to the output terminal 16 of the memory part 1 and a non-inverting input terminal connected to the output terminal 26 of the reference part 2. Further, the differential amplifier 31 has an output terminal connected to a data output terminal 32 of the memory device.
When reading data from the memory cell 14, the memory cell 14 is addressed in response to the column selection signal on the column bus 18 and the word line voltage on the word line WL, and the voltage on the bit line BL is changed depending on whether the data "1" is stored in the memory cell 14 or the data "0" is stored therein. The differential amplifier 31 produces either a low level output L in response to the output voltage V.sub.M of 4 volts corresponding to the data "0" stored in the memory cell 14 or a high level output H in response to the output voltage V.sub.M of 3 volts corresponding to the data "1" stored in the memory cell 14 on the basis of the comparison with the reference voltage V.sub.R which is set to be 3.5 volts as already described. In other words, the identification of the content of the data stored in the memory cell 14 can be performed on the basis of detection of the variation of the output voltage V.sub.M of only 1 volt. Thereby, a quick identification can be performed with respect to the content of the data and the access time for reading the data out from the memory cell 14 is significantly reduced.
In the foregoing conventional memory device, there arises a problem, associated with the requirement of miniaturization of the transistors forming the memory device, that a slight variation in the size of the memory cell, particularly the memory cell 24 in the reference part 2, with respect to the gate length or gate width, may cause a significant variation in the characteristic of the memory cell. When the reference voltage V.sub.R is changed, there is a substantial risk that an erroneous reading of the data is made or a relatively long time is needed in order to read the data with reliability.